Thyristors have been used as indispensable devices for large capacity power conversion due to their low on-voltage characteristics. Specifically, GTO (gate turn-off) thyristors are currently used very often in the high-voltage, large-current range applications. Drawbacks of the GTO thyristors, however, have also become clear. The drawbacks include the fact that the GTO thyristors require a large gate current for turning-off, that is a turn-off gain of the GTO thyristors is small, and the fact that the GTO thyristors require large snubber circuits for safe turn-off. In addition, the GTO thyristors are of limited use in a considerably low frequency range because of their slow switching speed.
In 1984, a MOS control thyristor (MCT) was proposed that may be classified into a voltage drive type device (See article by Temple, IEEE IEDM Tech. Dig., page 282). Since then, analysis and improvement of the MCT have been done world wide, since the MCT, which is a voltage driven type device, can be driven with a much simpler gate circuit than the GTO thyristors, and since the MCT turns on at a low on-voltage.
In addition, a novel device structure has been recently proposed that has double gate structures for turning on the device in a thyristor mode and for turning off the device in an IGBT mode (See article by S. Momota et al., Proceedings of IEEE ISPSD '92 (1992), P28, and article by Seki et al., Proceedings of IEEE ISPSD '93 (1993), P159).
FIG. 3 is a sectional view showing a DGMOS, the device proposed in 1992. In this device, an n- layer 23 is formed on a p.sup.+ collector layer 21 through an n.sup.+ buffer layer 22. A p-base region 24 is selectively formed in a surface layer of the n.sup.- layer 23, and n-base region 25 is selectively formed in a surface layer of the p-base region 24. A p-emitter region 26 is selectively formed in a surface layer of the n-base region 25. An emitter electrode 27, connected to an emitter terminal E, contacts commonly with the surfaces of the p-emitter region 26 and the n-base region 25. The first gate electrode 31 is disposed from above an area of the n-base region 25, sandwiched by the p-base region 24 and the p-emitter region 26, to above an exposed area of the n.sup.- layer 23 through a gate oxide film 28. The first gate electrode 31 is covered with an insulation film 29 and connected with the first gate terminal G.sub.1. The second gate electrode 32 is disposed from above an exposed area of the p-base region 24 and to above an area of the n-base region 25 sandwiched by the p-base region 24 and the p-emitter region 26 through the gate oxide film 28. The second gate electrode 32 is covered with an insulation film 29 and connected with the second gate terminal G.sub.2. The p.sup.+ collector layer 21 is connected with a collector electrode 30 which is further connected with a collector terminal C.
A voltage, the wave form of which is shown in FIG. 4, is applied to the first and the second gate electrodes 31 and 32. When voltage higher than a threshold value is applied to the terminal G.sub.1, an inversion layer is formed in a surface of the p-base region 24 under the gate electrode 31. An electron current, based on electrons which pass through the inversion layer, flows in the n.sup.- layer 23 and the n.sup.+ buffer layer 22. Since positive voltage is applied to the collector electrode 31, the electron current which flows in the built-in n.sup.- layer 23 and the n.sup.+ buffer layer 22 functions as a base current of a PNP transistor consisted of the p.sup.+ layer 21, the n.sup.+ buffer layer 22, the n.sup.- layer 23 and the p-base region 24. The electron current which has flown in the built-in PNP transistor modulates the conductivity of the n.sup.- layer 23 and turns on the PNP transistor. A hole current generated by the conductivity modulation functions as a base current of an NPN transistor and drives the NPN transistor which is consisted of the built-in n.sup.- layer 23, the n.sup.+ buffer layer 22, the p-base region 24 and the n-base region 25. Finally, a PNPN transistor, consisted of the p.sup.+ layer 21, the n.sup.+ buffer layer 22, the n.sup.- layer 23, the p-base region 24 and the n-base region 25, is driven to turned on the device from the terminal G.sub.1.
The device is turned off by switching off the voltage applied to the gate electrodes 31, 32 with a time gap between the electrodes 31 and 32 as shown in FIG. 4. Since the voltage of the gate electrode 32 grounded at time t.sub.1 becomes negative with respect to the voltage of the gate electrode 31, an inversion layer is formed in the surface under the gate electrode 32 of the n-base region 25 to turn on a p-channel MOSFET. When the p-channel MOSFET turns on through the terminal G.sub.1, the p-base region 24 and the n-base region 25 are short-circuited. Thus, the device structure becomes essentially equivalent to that of the IGBT.
Therefore, in a steady state operation, the device is operated at first as a thyristor through the gate electrode 31. The device is switched, at first when the device is turned off, from the thyristor mode to an on-state of an IGBT by applying a negative bias at time t.sub.1 to the gate electrode 32 with respect to the gate electrode 31. After 2 to 4 .mu.sec has elapsed since the device was switched to the IGBT operation mode, the device is turned off by stopping electron supply by switching off at time t.sub.2 the voltage applied to the gate electrode 31.
The DGMOS proposed in 1993 is a device which lowers on-resistance by replacing the p-channel device of FIG. 3 by an n-channel device. These devices are characterized by their dual modes which realize the low on-voltage of the thyristor and high speed switching of the IGBT in a single device.
However, since a large tail current is caused at switching in the MCTs as in the GTO thyristors, the MCTs are used also in a low frequency range. Further, the devices with two insulation structure cannot be practically used, since the current which the devices can control is small.
In view of the foregoing, an object of the present invention is to provide an insulated gate thyristor which facilitates with a single device controlling a large current and switching at high speed.